Presentation
Efficient Deployment of Irregular Computations on Multi- and Many-Core Architectures
Author
Advisor
Event Type
Doctoral Showcase
W
TUT
TP
EX
EXH
TimeWednesday, November 14th8:30am - 5pm
LocationC2/3/4 Ballroom
DescriptionMulti- and manycore processors have been advancing High Performance Computing with their high throughput and power efficiency. There has been an increasing interest in accelerating irregular computations on these devices that offer massive parallelism. My thesis focuses on compiler techniques and code transformations that facilitate the deployment of irregular computations on multi- and many-core processors, aiming to achieve higher performance and better programmability. My contributions are below. We propose a compiler-based consolidation framework to improve the efficiency of irregular graph and tree computations written with Dynamic Parallelism on GPUs. We analyze and categorize parallel recursive tree traversal patterns, then provide insights on how to select the platform and code template based on identified traversal patterns. We propose compiler techniques to support a SIMT programming model on Intel multi- and many-core architectures with wide vector units, and point out the main challenges in supporting the SIMT model, especially for irregular computations.
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