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LOCATION:D172
DTSTART;TZID=America/Chicago:20181112T090000
DTEND;TZID=America/Chicago:20181112T173000
UID:submissions.supercomputing.org_SC18_sess168@linklings.com
SUMMARY:IA^3 2018: 8th Workshop on Irregular Applications: Architectures a
 nd Algorithms
DESCRIPTION:Workshop\nArchitectures, Data Analytics, Graph Algorithms, Wor
 kshop Reg Pass\n\nSoftware Prefetching for Unstructured Mesh Applications\
 n\nHadade, Jones, Wang, di Mare\n\nApplications that exhibit regular memor
 y access patterns usually benefit transparently from hardware prefetchers 
 that bring data into the fast on-chip cache just before it is required, th
 ereby avoiding expensive cache misses. In contrast, unstructured mesh appl
 ications contain irregular access patte...\n\n---------------------\nWorks
 hop Morning Break\n\n\n\n---------------------\nPhotonic Interconnects for
  Extreme Scale Computing\n\nGlick\n\nThe capabilities of large-scale high 
 performance computing systems, either as supercomputers or warehouse scale
  data centers, are increasingly pervasive in different areas of modern lif
 e, from weather predictions to film and fashion recommendations. New appli
 cations using data intensive computations...\n\n---------------------\nVer
 sal: The New Xilinx Adaptive Compute Acceleration Platforms (ACAP)\n\nViss
 ers\n\nIn this presentation, I will present the new Adaptive Compute Accel
 eration Platform. I will show the overall system architecture of the famil
 y of devices including the Arm cores (scalar engines), the programmable lo
 gic (Adaptable Engines) and the new vector processor cores (AI engines). I
  will focus...\n\n---------------------\nWorkshop Lunch (on your own)\n\n\
 n\n---------------------\nWorkshop Afternoon Break\n\n\n\n----------------
 -----\nA Fast and Simple Approach to Merge and Merge Sorting Using Wide Ve
 ctor Instructions\n\nWatkins, Green\n\nMerging and sorting algorithms are 
 the backbone of many modern computer applications. As such, efficient impl
 ementations are desired. Recent architectural advancements in CPUs (Centra
 l Processing Units), such as wider and more powerful vector instructions, 
 allow for algorithmic improvements. This pa...\n\n---------------------\nI
 A^3 Debate\n\nFeo\n\nThe IA^3 oxfordian debate!\n\n---------------------\n
 Mix-and-Match: A Model-Driven Runtime Optimization Strategy for BFS on GPU
 s\n\nVerstraaten, Varbanescu, de Laat\n\nIt is universally accepted that t
 he performance of graph algorithms is heavily dependent on the algorithm, 
 the execution platform, and the structure of the input graph. This variabi
 lity remains difficult to predict and hinders the choice of the right algo
 rithm for a given problem.\n\nIn this work, we ...\n\n--------------------
 -\nImpact of Traditional Sparse Optimizations on a Migratory Thread Archit
 ecture\n\nRolinger, Krieger\n\nAchieving high performance for sparse appli
 cations is challenging due to irregular access patterns and weak locality.
  These properties preclude many static optimizations and degrade cache per
 formance on traditional systems. To address these challenges, novel system
 s such as the Emu architecture have...\n\n---------------------\nHigh-Perf
 ormance GPU Implementation of PageRank with Reduced Precision Based on Man
 tissa Segmentation\n\nGrützmacher, Anzt, Scheidegger, Quintana-Ortí\
 n\nWe address the acceleration of the PageRank algorithm for web informati
 on retrieval on graphics processing units (GPUs) via a modular precision f
 ramework that adapts the input data format in memory to the numerical requ
 irements as the iteration converges. In detail, we abandon the ieee 754 si
 ngle- a...\n\n---------------------\nThere Are Trillions of Little Forks i
 n the Road:  Choose Wisely! -- Estimating the Cost and Likelihood of Succe
 ss of Constrained Walks to Optimize a Graph Pruning Pipeline\n\nTripoul, H
 alawa, Reza, Sanders, Pearce...\n\nWe have developed [Reza et al. SC18] a 
 highly scalable algorithmic pipeline for pattern matching in labeled graph
 s and demonstrated it on trillion-edge graphs. This pipeline: (i) supports
  arbitrary search patterns, (ii) identifies all the vertices and edges tha
 t participate in matches - offering 100...\n\n---------------------\nIntro
 duction - IA^3 2018:  8th Workshop on Irregular Applications: Architecture
 s and Algorithms\n\nTumeo, Feo, Castellana\n\nDue to the heterogeneous dat
 a sets they process, data intensive applications employ a diverse set of m
 ethods and data structures, exhibiting irregular memory accesses, control 
 flows, and communication patterns. Current supercomputing systems are orga
 nized around components optimized for data localit...\n\n-----------------
 ----\nA Block-Oriented, Parallel, and Collective Approach to Sparse Indefi
 nite Preconditioning on GPUs\n\nThuerck, Naumov, Goesele, Garland\n\nLarge
  sparse symmetric indefinite matrices are notoriously hard to precondition
 . They often lack  diagonal dominance and exhibit Schur-complements that r
 ender zero fill-in factorization preconditioning ineffective. Pivoting, a 
 necessity for stable LDLt factorizations, complicates parallel approaches.
 ..\n\n---------------------\nScale-Free Graph Processing on a NUMA Machine
 \n\nAasawat, Reza, Ripeanu\n\nModern shared-memory systems embrace the NUM
 A architecture which has proven to be more scalable than the SMP architect
 ure. In many ways, a NUMA system resembles a shared-nothing distributed sy
 stem: physically distinct processing units and memory regions. Memory acce
 sses to remote NUMA domains are mo...\n
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